RISC-V — Open Silicon for Sovereign AIRISC-V—OpenSiliconforSovereignAI

Yes. RISC-V has moved well beyond academic experimentation. Tenstorrent's Blackhole chips, which power AGICY's Galaxy servers, are production-grade silicon running 24/7 AI inference workloads. SiFive has shipped billions of RISC-V cores in commercial products. The RISC-V specification has been stable since ratification, with the base integer ISA frozen to ensure backward compatibility. Major software toolchains (GCC, LLVM, Linux) have mature RISC-V support, and the AI framework ecosystem (PyTorch, ONNX) is fully functional on RISC-V through Tenstorrent's TT-Metalium SDK. AGICY's infrastructure targets 612,000 tokens per second in production — the maturity question has been definitively answered by real-world performance data.

Tenstorrent's Blackhole RISC-V chips take a fundamentally different architectural approach than NVIDIA GPUs. Rather than relying on thousands of small shader cores with shared memory, Blackhole uses Tensix engines for matrix compute, plus sixteen Linux-capable RISC-V cores and ~752 baby RISC-V cores per chip. Do not write “RISC-V Tensix cores” as one blob. This architecture is designed for throughput per watt on AI inference — a Galaxy server is air-cooled in the 8–10 kW operating band (not 9 kW nameplate; ~12 kW max). Fleet-scale throughput figures are planning targets, not a single-server measurement. Tensix engines are more efficient than general-purpose GPU shader cores on transformer attention patterns and matrix operations because they are purpose-built for that work.

AGICY's infrastructure provides an OpenAI-compatible API that abstracts the underlying hardware entirely — your application code doesn't need to know whether it's running on RISC-V or any other architecture. For customers who need deeper hardware access, Tenstorrent's TT-Metalium SDK provides PyTorch and ONNX Runtime integration, enabling direct model deployment on RISC-V silicon. All major open-weight models (Llama 4, Mistral, DeepSeek, Qwen, Gemma) are pre-optimized for Tenstorrent hardware in AGICY's model library. The transition from CUDA-based infrastructure to RISC-V is seamless at the API level and requires minimal effort at the framework level, with comprehensive documentation and migration guides provided by AGICY's engineering team.

The European Chips Act explicitly identifies open instruction set architectures like RISC-V as strategic technologies for achieving European digital sovereignty. Unlike x86 (controlled by US corporations Intel/AMD) or ARM (controlled by SoftBank/Japan), RISC-V is governed by a Swiss-based non-profit foundation, making it neutral to any single government's trade policies. The EU has funded multiple RISC-V initiatives including the European Processor Initiative (EPI) and various Horizon Europe research programs. AGICY's RISC-V infrastructure directly implements the EU's vision of sovereign AI compute — infrastructure that European organizations can rely on without dependency on US technology companies, US export controls, or US government data access authorities like the CLOUD Act.