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STATUS: PRE-CONSTRUCTION · SITE A UNDER EXCLUSIVITYNODE: VASILIKOS-01 — 34.7246°N, 33.2247°ECAMPUS: RISC-V PHASE 1 · MULTI-SILICON EVAL · PLANNEDPOWER: 42MW ON-SITE GENERATION · DESIGN TARGETSTATUS: PRE-CONSTRUCTION · SITE A UNDER EXCLUSIVITYNODE: VASILIKOS-01 — 34.7246°N, 33.2247°ECAMPUS: RISC-V PHASE 1 · MULTI-SILICON EVAL · PLANNEDPOWER: 42MW ON-SITE GENERATION · DESIGN TARGET
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§ 00CorsairOverview§ 01ThesisDecode lane§ 02ArchitectureDIMC§ 03LatencySub-2 ms§ 04GalaxyCompare§ 05FacilityPhase 2–3§ 06DiligenceOpen items§ 07AGICYRelevance
Sheet 00 · Plan viewAGICY-DM-001

Hardware · d-Matrix Corsair · Pre-COD

d-Matrix Corsair

DIMC for low-latency decode

Phase 2–3 evaluation at AGICY Vasilikos — silicon optionality, not endorsement

d-Matrix Corsair is a digital in-memory compute (DIMC) inference accelerator aimed at the memory-bandwidth-bound decode phase — not a wholesale replacement for Tenstorrent Galaxy or GPU prefill clusters. Investor digest status: Evaluation · Phase 2–3for a sub-2 ms decode lane. Phase 1 capital planning remains Galaxy.

  • Digital In-Memory Compute
  • Decode-lane focus
  • Pairs with GPU / LPU prefill
  • Phase 2–3 · on Watchlist
  • No d-Matrix endorsement
  • Vendor / lab figures under diligence
  • Not Phase 1 capital plan
  • Pre-COD · roadmap optionality
Decode thesisvs GalaxyDiligenceResearch deep dive
d-Matrix Corsair PCIe DIMC accelerator cardElevation · Corsair PCIe · Phase 2–3 eval
DIMCArchitecture
<2 msDecode lane (eval)
PCIeCard form factor
P2–3Eval · not CapEx
Sheet 01 · ThesisDecode lane

Attack the memory wall

Prefill is compute-heavy; decode is memory-bound. Corsair targets the second problem with DIMC.

Research disclaimerThroughput and latency figures marked vendor-claimed or lab-reported require independent validation. d-Matrix is evaluated as Phase 2–3 silicon optionality — not a strategic partner endorsing AGICY's financial model. No exclusive d-Matrix supply contract is claimed. Campus pods are pre-COD plans, not live capacity.
Verified · architecture classVendor / lab · performance

Autoregressive decode re-reads weights and KV state for every token. DIMC keeps compute next to on-chip / near-memory SRAM so the accelerator spends less energy shuttling parameters across a conventional memory bus.VENDOR-CLAIMED

Industry deployments often disaggregate: GPUs (or other XPUs) handle prefill; Corsair-class cards take decode / speculative-decode lanes. That is complementarity — not a claim that Corsair replaces Galaxy fleet economics.VERIFIED

Next: DIMC architecture →

Sheet 02 · ArchitectureDIMC · Corsair

Digital in-memory compute

Fully digital IMC — deterministic numerics — in a data-center PCIe / rack attach form factor.

  • DIMC performs matrix ops close to SRAM rather than treating HBM as a remote warehouseVENDOR-CLAIMED
  • Designed for heterogeneous clusters (prefill elsewhere, decode on Corsair)VENDOR-CLAIMED
  • Public vendor communications (2026) describe Corsair entering production / volume shipping to priority customers — still not AGICY Phase 1 capital baselineVENDOR-CLAIMED
d-Matrix Corsair dual-width accelerator card
Corsair PCIe card · vendor photography
d-Matrix Corsair chiplet / 3DIMC feature graphic
3DIMC chiplet · vendor graphic

Deep dive: d-Matrix Corsair research article →

Next: Latency ledger →

Sheet 03 · Performance ledgerDecode latency

Sub-2 ms decode lane

AGICY digest framing for this technology card — independent validation pending before CapEx.

Digest · eval chipLab / vendor · speedups
Claim classStatus at AGICYNotes
Sub-2 ms decode laneEvaluation · P2–3Investor digest silicon portfolio chip — not installed capacity
Heterogeneous GPU + Corsair speedupsLab / vendor-reportedIndependent blogs cite large end-to-end latency cuts; diligence required
Phase 1 CapEx / P&LGalaxy capital plan onlyCorsair does not underwrite Round 1 fleet math

Next: Corsair vs Galaxy — different problems →

Sheet 04 · ComparisonCorsair vs Galaxy

Corsair vs Galaxy — different problems

Galaxy is the Phase 1 fleet anchor. Corsair is a specialized decode accelerator under evaluation.VERIFIED

d-Matrix Corsair

  • DIMC decode / interactivity lane — often paired with separate prefill siliconVENDOR-CLAIMED
  • Phase 2–3 evaluation — complementary, not a Galaxy substitute
  • Not Phase 1 capital / P&L baseline

Tenstorrent Galaxy

  • Modular open RISC-V servers for sovereign batch and civil inference at fleet scaleVENDOR-CLAIMED
  • Air-cooled Phase 1 capital / P&L baseline
  • Primary underwriting silicon (pre-COD)

Also on the queue: Cerebras CS-3 (wafer-scale), IBM z17 (AI next to the ledger), and AMD Helios (open rack-scale).

Next: Vasilikos Phase 2–3 fit →

Sheet 05 · FacilityPhase 2–3 fit

Vasilikos Phase 2–3 facility fit

PCIe / rack-attach decode cards can sit beside fleet floors — still gated by selection and Financial Close.

Technology page maps Corsair into the Token Factory narrative as a decode-lane evaluation, not as day-one CapEx. Power, networking, and software (Aviator runtime class) diligence precede any purchase order.DESIGN TARGET

d-Matrix Corsair and JetStream rack-scale Ethernet fabric diagram
SquadRack / JetStream scale-out · vendor diagram · illustrative (not Vasilikos)

Sovereign AI Campus briefing →

Next: Diligence & honesty →

Sheet 06 · DiligenceHonesty ledger

Diligence & honesty

What AGICY claims — and what it does not — about d-Matrix on campus.

AGICY honesty checkPhase 1 capital, P&L, and fleet planning are anchored on Tenstorrent Galaxy. d-Matrix Corsair is Evaluation · Phase 2–3. Do not read this page as installed Corsair capacity, a d-Matrix endorsement, or a signed exclusive supply contract.VERIFIED
  • No signed exclusive d-Matrix supply contractVERIFIED
  • Lab / vendor latency speedups pending AGICY-independent SC-class validationDESIGN TARGET
  • Software maturity and heterogeneous cluster ops are standard pre-production risksDESIGN TARGET

Next: AGICY relevance (pre-COD) →

Sheet 07 · DeploymentAGICY relevance

AGICY relevance

Multi-silicon sovereign posture (pre-COD) — decode-lane optionality beside the Galaxy Phase 1 anchor.

Phase 2–3 decode-lane optionality (pre-COD)Galaxy for sovereign batch and civil inference economics; Corsair where interactive decode latency gates favour DIMC. Vendor-neutral campus, workload-aware routing. d-Matrix remains a silicon evaluation option — not an endorsing partner.VERIFIED

Interested in Leasing?

Lease or finance d-Matrix units on AGICY premises, or at your site if it meets our T&Cs. Free estimate for integration and delivery (quote-only). Pre-COD; Leasing ≠ SRA / CY tokens.

Interested in Leasing?Contact hardware teamTenstorrent GalaxyResearch article
Tenstorrent GalaxyCerebras CS-3IBM z17 / LinuxONE 5AMD HeliosTechnology stackCopperway gateway

§ FIN — Close of Document

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Schedule a confidential briefing with our team. NDA-protected, no commitment.

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